This invention relates to a semiconductor memory device that contains a plurality of associative memories.
In recent years, there has been a tendency that many high-speed, large scale integrated semiconductor memory devices contain a plurality of associative memories. Typical associative memories include a translation look-aside buffer (TLB) to support virtual memory system, and a cache memory to achieve a fast access to data, particularly one that is accessed by physical addresses. Full-associative system has increasingly been employed because of its high hit rate. Meanwhile, a microprocessing unit (MPU), composed of a central processing unit (CPU) and a semiconductor memory unit with plural associative memories mounted on the same chip, is also used in many applications.
As an example, one principal operation of an MPU containing a TLB and a cache memory is described below. A logical address is first issued to the TLB. The TLB in return outputs a physical address corresponding to the logical address. Such a physical address is supplied to a tag memory in the cache memory. Data corresponding to the physical address is output from a data memory in the cache memory. For the above-described MPU containing the TLB and the cache memory, the transmission of the physical address from the TLB to the cache memory (i.e., the data transmission from one associative memory to another) is required.
However, the TLB and the cache memory are conventionally regarded as different, independent functional blocks, and they are kept separate at different locations within a chip. Data transmission time necessary for transmitting data from the TLB to the cache memory has been one of the causes that prevent the MPU from operating at high speed. Further, a large wiring area is inevitably required for connection between the TLB and the cache memory, which is an obstacle to the improvement of the integration of semiconductor memory device.
Therefore, a principal aim of the present invention is that, in a semiconductor memory device incorporating therein a plurality of associative memories, high-speed data transmission between the associative memories is accomplished while having the integration of semiconductor memory device improved.